Qartographer: A Novel Approach to Quantum Chip Design

ABSTRACT

This paper presents Qartographer, an open-source Python framework for the design and optimization of ancillary control layouts in quantum processors. This computational tool addresses the critical challenge of creating compact, high-performance designs by systematically arranging control and readout lines. It employs a multi-objective cost function to optimize wire paths, and this process is engineered to efficiently converge to the optimal solution for the system at hand.

INTRODUCTION.

The promise of quantum computing to revolutionize fields from cryptography to materials science has driven a global effort to build powerful, scalable quantum computers. Unlike classical computers that store information in bits, quantum computers use quantum bits, or qubits—two-level quantum systems that can exist in a superposition, or blend, of their basis states and be entangled with one another—offering the potential for exponential speedups on certain computational problems. This transformative potential was first highlighted by landmark theoretical breakthroughs, such as Shor’s algorithm for factoring large numbers [1] and Grover’s algorithm for unstructured search [2]. These foundational works sparked intense interest and laid the groundwork for the field of quantum information science, as comprehensively detailed in the seminal textbook by Nielsen and Chuang [3].

In superconducting quantum processors, qubits are fabricated as nonlinear microwave circuits on a cryogenic chip and are manipulated using precisely timed microwave control pulses. Each qubit is coupled to dedicated control lines for state manipulation and to resonant readout circuitry for measurement. These ancillary components, namely control lines, readout resonators, and multiplexed transmission lines that combine signals from multiple qubits, occupy substantial chip area and must be routed carefully to mitigate electromagnetic crosstalk, parasitic coupling, and excess signal loss.

While theoretical research has progressed, a significant bottleneck remains in designing and optimizing the physical chip layout. Crafting a quantum chip is a complex puzzle, requiring not only the careful placement of qubits but also the precise routing of control and readout lines. Improper routing can introduce crosstalk, unwanted interference between qubits, and signal interference, compromising processor performance [4].

As quantum processors scale, the need for automated design tools becomes critical, especially as systems transition from a handful of qubits to the thousands or even millions required for practical quantum algorithms [5]. The manual routing of these control components is a tedious and time-consuming task. Since the number of connections grows quadratically, this manual approach leads to an increased risk of crosstalk and signal interference.

To tackle these issues, I developed Qartographer, a computational tool that automates the wire routing process. Qartographer focuses on optimizing the layout of ancillary components, providing a streamlined workflow for exploring scalable, high-performance quantum processor designs.

While recent developments [6] have been made towards Quantum Electronic Design Automation (EDA) software, they do not directly target the optimization of ancillary control and readout systems routing. Qartographer is designed specifically to fill this gap by proposing compact, organized wiring patterns, thereby making it easier to explore scalable chip designs and offering a more targeted solution to the control-layout bottleneck in superconducting quantum processors.

MATERIALS AND METHODS.

My approach uses an optimization framework to systematically design and refine quantum chip layouts. It starts with a pre-optimized qubit layout, followed by optimization of the readout components and, subsequently, the control lines. The results generated by the optimization steps are encoded into a structured JSON file. The user can then employ the Merger tool to combine and manage this data, resulting in a complete, ready-to-use quantum chip blueprint. This JSON modularity lets researchers developing quantum chips flexibly adjust individual layout components, ensuring the design can be efficiently adapted to evolving fabrication constraints.

Optimization process.

The optimization framework initiates the routing process by addressing the qubit measurement and readout systems. The complexity of a large-scale quantum processor necessitates separating the optimization of the dense readout circuitry from the individual control lines.

Readout systems routing.

This step is formulated as a minimization problem, seeking the optimal start and end coordinates for a readout multiplexer line segment by minimizing a composite cost function, which enforces efficient connections to the qubits and line compactness. The Readout Line Alignment term aligns the individual readout resonators with the main multiplexer line by enforcing a specific, ideal length ( )  for the readout lines connecting each qubit to the closest point on the multiplexer; the penalty, weighted by the factor , is calculated as the sum of squared errors (SSE) between the ideal line length and the actual distance from each qubit to the nearest multiplexer segment. Additionally, a Length Cost penalty, proportional to the square of the multiplexer line length and weighted by  promotes a compact design by minimizing space and passive signal loss. To prioritize a smaller chip footprint, one can increase the weight , while increasing the other weight (  will favor adherence to the ideal targeted readout length.

The resulting positions for the multiplexer lines are then treated as stagnant geometric obstacles for the subsequent drive line optimization stage. This ensures that the high-density, relatively fixed readout infrastructure is laid out efficiently before tackling the more variable individual control paths.

Control line routing.

The routing process takes a fixed qubit layout and the Drive Sub Miniature Push-on Micro (SMPM) connection points, then designs the paths for the drive and readout lines. Qartographer achieves this by minimizing a multi-objective cost function that balances several key design constraints. A gradient-based optimizer is well-suited for this task because the routing cost function is generally smooth and differentiable under typical layout conditions.

The cost function is a composite of three key terms. The Proximity Penalty penalizes control lines that pass too close to qubits or to each other, helping prevent unwanted crosstalk and signal interference. The Length Cost minimizes the length of the multiplexer and drive lines to reduce signal loss and latency, thereby promoting high-fidelity operations. Finally, the Readout Line Alignment term encourages readout lines to connect efficiently from each qubit to its nearest multiplexer line, targeting an ideal line length. Each of these penalties can be weighted to emphasize different aspects of the chip structure, and choosing the best weight values for the task at hand is critical for the usage of this tool.

For the optimization process, I decided to use the L-BFGS-B algorithm [7], a memory-limited version of the Broyden-Fletcher-Goldfarb-Shanno algorithm through SciPy [8]. The L-BFGS-B algorithm was chosen to handle the large number of variables in the routing problem efficiently, avoiding the computational inefficiency of a full-memory algorithm.

JSON file structure.

The Qartographer workflow uses a structured JSON format to store and transfer data. This modular design helps in managing the data for different stages of the design process.

1. Qubit Placement Data File: This input file contains the pre-optimized qubit arrangement. It contains:
   • optimized_qubit_coordinates: A dictionary mapping each qubit (e.g., “Qubit_0”) to its final x and y coordinates.
   • optimized_couplings: A list of objects representing couplings between qubits, specifying the qubit1_index and qubit2_index.
2. Wiring Data File: This is the primary output file from the ancillary component routing process. It details the paths for all control/readout lines and includes:
   • fixed_drive_points: Coordinates for the fixed endpoints of drive lines on the chip boundary.
   • optimized_multiplexer_lines: Endpoints of optimized multiplexer lines.
   • optimized_readout_to_multiplexer_lines: Connections from each qubit to a multiplexer line.
   • optimized_drive_paths: Optimized routes of drive lines from each qubit to its drive point.

The Qartographer tool suite.

Beyond the core optimization algorithms, Qartographer includes a suite of tools for managing the design workflow. This suite, comprising of a merger, a splitter, and a plotter, ensures a modular and robust process.

1. Merger: The merger combines data from the qubit placement and wiring files into a single, comprehensive device map JSON. This creates a unified blueprint for the entire chip layout known as a device map. This file serves as a complete blueprint of the entire quantum chip, consolidating all information into one file for easy use
2. Splitter: The splitter performs the inverse operation, taking a unified device map and separating it into its constituent JSON files. This is useful for iterative design; for instance, a designer can extract only the wiring data to perform a new round of routing without affecting the existing qubit couplings. This modularity allows for focused exploration and modification.
3. Plotter: The plotter visualizes the chip layout from a device map JSON file. It displays qubit locations, couplings, and the intricate routes of all control lines. This visual feedback is essential for design verification, helping designers quickly spot potential issues like overcrowding or closely routed lines that could cause crosstalk.

RESULTS.

The Qartographer tool successfully optimizes control line layouts for quantum processors, as demonstrated by applying the methodology to various qubit array configurations. I specifically tested the framework on two distinct square lattice sizes: a 3×3 array (9 qubits, Figure 2) and a 5×5 array (25 qubits, Figure 3). In both cases, the optimization process effectively minimized the composite cost function across the large number of variables that define the wire paths. For the 3×3 instance, the full optimization completed in 15.5518 ± 0.5154 seconds on an Intel® Core™ i7-1195G7 (4 cores, 8 threads, 2.90 GHz, 64-bit)[9], running alongside 16 GB of DDR4 RAM (3200MHz).

 

For the 3×3 array, the optimization achieved a compact and efficient arrangement. The minimal crossing count among the drive paths and readout/multiplexer lines facilitated a rapid convergence to the global minimum. While the smaller array appeared to reach a global minimum efficiently, the 5×5 array highlights the increased complexity of larger systems. The multi-objective cost function enabled balanced optimization, but tuning the weights of proximity penalty, length cost, and readout alignment remains a critical hyperparameter that requires further study. For the 5×5 instance, the optimization required 42.7815 ± 0.0.8479 seconds on the same Intel® Core™ i7-1195G7 (4 cores, 8 threads, 2.90 GHz, 64-bit) processor and 16 GB of DDR4 RAM, reflecting the increased computational complexity of larger layouts.

DISCUSSION.

While the Qartographer tool effectively optimizes control line layouts, several areas for improvement can be explored in future work. The current framework optimizes idealized wire paths, so a critical next step is to integrate real-world fabrication constraints directly into the cost function. This includes adding penalties for sharp turns, minimum trace widths, and other lithography-related limitations to make designs more robust and manufacturable. Additionally, incorporating more sophisticated physical models, such as calculating capacitance or inductance between wires, would improve the designs’ physical accuracy by allowing the optimizer to minimize crosstalk and other noise sources more directly. Future research could also extend the framework to include readout multiplexer SMPM port integration, a crucial step toward generating designs more directly translatable to physical fabrication.

The Qartographer project provides a foundational framework for tackling the automated physical design of quantum processors. Future research can build upon this foundation by extending the core capabilities to address more complex, real-world design problems. These research directions can be explored as independent modules or as part of a more comprehensive, integrated design system.

One area of improvement is the integration of physical models into the optimization process. For example, a module could be developed to calculate mutual inductance and capacitance between wire segments, providing a more accurate measure of crosstalk. The output of this module could be incorporated as a penalty term in the cost function, allowing the optimizer to minimize physical noise sources more directly.

Another promising direction is the development of constraint-aware optimization. The current tool does not account for many fabrication-specific constraints. A valuable research project would be to develop a constraint-aware optimization layer. This would involve building a set of rules and penalties for lithography-related limitations, such as minimum wire spacing, realistic traces, bend radii, and layer restrictions. The optimization would then find the most efficient layout that adheres to a given fabrication process’s design rules, producing designs that are not just theoretically optimal but also physically manufacturable.

Algorithmic scalability also represents a critical area for future research. As quantum processors scale to thousands of qubits, the dimensionality of the optimization problem will grow quadratically. A critical area of research is to investigate and implement more scalable optimization algorithms. This could include developing specialized decomposition techniques to break the problem into smaller, more manageable sub-problems, or exploring the application of machine learning methods, such as deep reinforcement learning, to discover routing strategies that generalize to large-scale systems.

Open-source collaboration would accelerate these extensions to the framework, enabling faster iteration, broader validation, and ultimately more practical, fabrication-ready quantum processor layouts.

CONCLUSION.

Qartographer is a robust computational tool for optimizing the wire layout in quantum processors. By leveraging SciPy’s optimization module and a carefully crafted multi-objective cost function, Qartographer automates a complex and critical aspect of quantum chip design. The tool’s modular architecture, supported by its merger, splitter, and plotter components, provides a flexible and repeatable workflow for exploring scalable, high-performance designs. As quantum hardware continues to evolve, the Qartographer framework offers a powerful solution to overcome the bottleneck of physical design, paving the way for more compact, efficient, and higher-fidelity quantum computers.

ACKNOWLEDGMENTS.

I would like to thank the Vanderbilt Collaborative for STEM Education and Outreach for the opportunity to publish my research, and Ari Noori for his input on practical quantum engineering considerations.

SUPPORTING INFORMATION.

Source code and documentation for the Qartographer framework is available at www.github.com/AYDOSUL/Qartographer.

A JSON guide for Qubit layout is available at www.github.com/AYDOSUL/Qartographer‌/blob/main/Documentation/JSONguide.md.

REFERENCES

1. P. W. Shor, Algorithms for quantum computation: Discrete logarithms and factoring. in Proceedings of the 35th Annual Symposium on Foundations of Computer Science (IEEE Computer Society, 1994), pp. 124–134.
2. L. K. Grover, A fast quantum mechanical algorithm for database search. in Proceedings of the Twenty-Eighth Annual ACM Symposium on Theory of Computing (ACM, 1996), pp. 212–219.
3. M. A. Nielsen, I. L. Chuang, Quantum Computation and Quantum Information (Cambridge University Press, 10th Anniversary ed., 2010).
4. V. Tripathi, et al. Suppression of crosstalk in superconducting qubits using dynamical decoupling. Physical Review Applied 18, 024068 (2022).
5. C. Gidney, M. Ekerå, How to factor 2048 bit RSA integers in 8 hours using 20 million noisy qubits. Quantum 5, 433 (2021).
6. B. Zhao, et al. EDA-Q: Electronic design automation for superconducting quantum chip. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 45, 266–279 (2026).
7. C. Zhu, R. H. Byrd, P. Lu, J. Nocedal, Algorithm 778: L-BFGS-B: Fortran subroutines for large-scale bound-constrained optimization. ACM Transactions on Mathematical Software. 23, 550–560 (1997).
8. P. Virtanen, et al. SciPy 1.0: Fundamental Algorithms for Scientific Computing in Python. Nature Methods 17, 261–272 (2020). DOI: 10.1038/s41592-019-0686-2.
9. Intel, “Intel® Core™ i7-1195G7 processor (12M cache, up to 5.00 GHz) specifications” (Intel Corp., 2021); https://www.intel.com/content/www/us/en/products/sku/217187/intel-core-i71195g7-processor-12m-cache-up-to-5-00-ghz/specifications.html

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Posted by buchanle on Friday, June 5, 2026 in May 2026.

Tags: Framework, optimization, Quantum Computing, Quantum Processors, SciPy, Software, Superconducting Qubits